Control store address generation logic for a data processing sys

Details Control store address generation logic for a data processing sys Control store address generation logic for a data processing sys

1979-01-03

1980-09-23

Nusbaum, Mark E.

Boots, shoes, and leggings

G06F 920

Patent

active

042246687

ABSTRACT:
A control store in a data processor is addressed by means of next address generation logic which includes a first multiplexer utilized to address the control store, which multiplexer has several inputs. One of such inputs is received from a latching mechanism which allows more than one test condition to be simultaneously utilized for addressing the control store on a free flow basis. These test conditions, as well as information from an addressed control word, are utilized in a multiplexed arrangement as one input of the first multiplexer. By use of other inputs of such first multiplexer, the control store may be addressed by use of branch address information, as well as other test condition information. A page register provides the page address, to a plurality of pages included in this control store with the locations in each such page addressed by use of the above noted multiplexer combination.

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patent: 4099229 (1978-07-01), Kancler

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