Processor and method for speculatively executing an instruction

Details Processor and method for speculatively executing an instruction Processor and method for speculatively executing an instruction

1996-07-22

1998-04-14

Donaghue, Larry D.

39580023, G06F 1582, G06F 932

Patent

active

057404194

ABSTRACT:
A processor and method for speculatively executing an instruction loop are disclosed. In accordance with the method, the processor initiates execution of an instruction loop and counts each executed iteration of the instruction loop. Thereafter, an actual number of iterations that the instruction loop should be executed is determined. In response to the determination, a difference between the actual number of iterations that the instruction loop should be executed and the number of executed iterations is determined. In response to a determination that the difference is greater than zero, the instruction loop is executed an additional number of iterations equal to the difference. According to one embodiment, unexecuted fetched instructions within mispredicted iterations of the instruction loop are cancelled in response to a determination that the difference is less than zero. In addition, data results of mispredicted iterations of the instruction loop that have been executed are discarded. In accordance with another embodiment, the executed iterations of the instruction loop are counted by setting a count register to zero and decrementing the count register once for each iteration of the instruction loop executed. The difference between the actual number of iterations that should be executed and the number of executed iterations is determined by adding the actual number of iterations and the value of the count register.

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Farrens et al. "A Comparison of Superscalar and Decoupled Access/Execute Architecture" IEEE, 1993.

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