Patent
1996-03-29
1998-04-14
Shah, Alpesh M.
39580001, G06F 900
Patent
active
057404186
ABSTRACT:
A pipelined processor includes a main memory, an instruction cache, a BTB, and a BTB registration discriminator for decoding instructions line fetched from the main memory at the time of mishit of the instruction cache and for registering branch information in the BTB when the instruction is a branch instruction. Since the branch information is already stored in the BTB even at the first execution time of the branch instruction, a branch prediction hit ratio is improved.
REFERENCES:
patent: 5440704 (1995-08-01), Itomitsu et al.
patent: 5471597 (1995-11-01), Byers et al.
patent: 5506976 (1996-04-01), Jaggar
patent: 5507028 (1996-04-01), Liu
patent: 5515518 (1996-05-01), Stiles et al.
patent: 5522053 (1996-05-01), Yoshida et al.
patent: 5530825 (1996-06-01), Black et al.
patent: 5623614 (1997-04-01), Van Dyke et al.
"Computer Architecture: A Quantitative Approach" by David A. Patterson et al., Morgan Kaufmann Publishers, Inc. 1990.
Mitsubishi Denki & Kabushiki Kaisha
Shah Alpesh M.
LandOfFree
Pipelined processor carrying out branch prediction by BTB does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pipelined processor carrying out branch prediction by BTB, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined processor carrying out branch prediction by BTB will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-647156