Multiprocessor system having a processor invalidating operand ca

Details Multiprocessor system having a processor invalidating operand ca Multiprocessor system having a processor invalidating operand ca

1993-01-26

1998-04-14

Chan, Eddie P.

395450, 395453, 395482, 395477, 395478, 395471, G06F 1214, G06F 1208

Patent

active

057404011

ABSTRACT:
A multiprocessor system includes an address bus 170, a data bus 180, processors 110 and 120, access queues 135 and 145, shared memories 130 and 140, and lock control circuits 500 and 510. Particularly, a lock-in indicative flag register 501 is provided in the lock control circuit 500. While an operand cache 112 in one processor 110 is making a lock access to a predetermined address of the shared memory 130, the flag register 501 is set on the basis of a lock command signal 260 so that an access of an instruction cache 122 in another processor 120 to the predetermined address of the shared memory 130 is prohibited but an access to a different address is permitted at the time of the lock access. After the lock access is released, the lock control circuit 500 accepts an access to the predetermined address.

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