High speed frequency divider circuit

Details High speed frequency divider circuit High speed frequency divider circuit

1990-01-25

1991-04-30

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Pulse counting or dividing chains

377105, 377111, H03K 2344

Patent

active

050124978

ABSTRACT:
A frequency divider receives a first frequency signal and at least one clock signal of a sub-multiple of the first frequency. The first frequency signal charges a storage terminal once each first frequency cycle and the sub-multiple frequency signal discharges the storage temrinal once each sub-multiple frequency cycle. The discharged storage terminal sets the frequency divider output which is reset by the first frequency signal when the storage terminal is discharged. The sub-multiple frequency clock signal is employed to control the storage terminal instead of a feedback path from the output to increase the operating frequency of the divider.

REFERENCES:
patent: 3707071 (1972-12-01), Walton
patent: 4002926 (1977-01-01), Moyer
patent: 4025800 (1977-05-01), Wanlass
patent: 4369379 (1983-01-01), Hull
patent: 4606059 (1986-08-01), Oida
patent: 4715052 (1987-12-01), Stambaugh
"CMOS Frequency Divider", IBM Technical Disclosure Bullentin, vol. 29, No. 6, Nov. 1986, pp. 2559-2560.

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