Reducing cache snooping overhead in a multilevel cache system wi

Details Reducing cache snooping overhead in a multilevel cache system wi Reducing cache snooping overhead in a multilevel cache system wi

1995-06-05

1998-04-14

Swann, Tod R.

395473, G06F 1200

Patent

active

057404003

ABSTRACT:
A memory system for reducing cache snooping overhead for a two level cache system with multiple bus masters, wherein the level 2 cache is connected to a main memory and wherein the level 1 cache is connected to a bus master. For each bus master, there is one level 1 cache assigned to it, and there is a shared level 2 cache that each of the level 1 caches are connected to. The level 2 cache has an inclusion field for each storage location within the level 2 cache. The inclusion field indicates if information held in a storage location associated with the inclusion field is contained in any of the level 1 caches connected to the shared level 2 cache. If there is a cache hit in the level 2 cache, the level 2 cache determines from the inclusion field that corresponds to the cache hit if the tag-address corresponding to the memory access of the bus master also resides in a level 1 cache assigned to a different bus master than the one that made the memory access. If so, the shared level 2 cache obtains the data from the level 1 cache assigned to the other bus master, and that data is read into the level 2 cache. The data is then read from the shared level 2 cache into the level 1 cache assigned to the bus master that initiated the memory access.

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