Optional single or double clocked latch

Details Optional single or double clocked latch Optional single or double clocked latch

1985-11-29

1990-01-23

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, H03K 3356

Patent

active

048960543

ABSTRACT:
This is related to a logic circuit which requires a double clocking latch during testing of the circuit to prevent race or flushing of the scan rings from occuring during the test mode and yet can be operated to capture and hold output data during the operation mode with stable data inputs. The preferred embodiment is a programmable latching circuit comprising a double ended cross coupled circuit having an input and an output and having first and second programmable legs and a third non-programmable leg with the first programmable leg cross coupled to the third leg and the second programmable leg being switchably cross coupled to the third leg.

REFERENCES:
patent: 4334157 (1982-06-01), Ferris
patent: 4387294 (1983-06-01), Nakamura et al.
patent: 4395645 (1983-07-01), Pernyeszi
patent: 4477738 (1984-10-01), Kouba
patent: 4495629 (1985-01-01), Zasio et al.
Millman and Halkias, Integrated Electronics: Analog and Digital Circuits and Systems, McGraw-Hill Book Co., New York, 1972, pp. 311-312, 327-328, 331-335.
Taub and Schilling, Digital Integrated Electronics, McGraw-Hill Book Co., New York, 1977, pp. 260-262, 268-269.
Mead and Conway, Introduction to VLSI Systems, Addison-Wesley Pub. Co., Reading, Mass., Oct. 1980, pp. 256-257.

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