Semiconductor memory device

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Details

357 41, H01L 2978, H01L 2992, H01L 2702

Patent

active

050123084

ABSTRACT:
A dynamic random access memory has a semiconductive substrate in which grooves are formed such that each groove has side walls and a bottom portion and which has a predetermined conductivity type. Each memory cell formed on the substrate has a transistor and a capacitor buried in the groove. The capacitor is constituted by a first conductive layer and a second conductive layer. The first conductive layer is connected to a source region of the transistor and has a layer portion extending in the groove along the side wall thereof. The second conductive layer is insulated from the first conductive layer, buried in the groove to oppose the first conductive layer and allows the conductive layer to store charge carriers in response to a voltage applied between the first and second conductive layers. The second conductive layer serves as a common electrode for all the memory capacitors formed on the substrate.

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