Digital counter test circuit

Details Digital counter test circuit Digital counter test circuit

1996-12-03

1998-04-14

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Identifying or correcting improper counter operation

H03K 2140

Patent

active

057402191

ABSTRACT:
A system for testing a digital counter of mn stages, in which the counter is organized into m segments, each of n bits, includes a two input exclusive OR gate connected between each of the m segments. One of the two inputs of each exclusive OR gate is obtained from the carry output of a lower order one of the m segments, and the output of each exclusive OR gate is connected to the carry input of the next higher order one of the m segments. The other inputs to the exclusive OR gates are obtained from a test signal enable input, which is driven high (binary "1") for the test mode of operation. The counter is fully exercised in the test mode in a parallel operation, with full testing of the carry bits from one segment to the next, without any interruption in the clock signal input stream.

Affiliated with

Also associated with

Rating

Digital counter test circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital counter test circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital counter test circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-643988