Error checking and correcting for burst DRAM devices

Details Error checking and correcting for burst DRAM devices Error checking and correcting for burst DRAM devices

1996-05-29

1998-04-14

Baker, Stephen M.

Excavating

G06F 1110

Patent

active

057401888

ABSTRACT:
A method is described of detecting and correcting errors in a computer having a memory subsystem including a burst DRAM device. The method includes the steps of beginning a write operation of N data bits to the burst DRAM device, generating M check bits from the N data bits, writing the N data bits and the M check bits to the burst DRAM device, reading the N data bits and M check bits from the burst DRAM device, generating X syndrome bits from the N data bits and the M check bits, and using the X syndrome bits to detect and correct any single bit error within the N data bits and the M check bits and to detect any double bit error within the N data bits and the M check bits. A computer system is also described having a central processing unit and a memory subsystem. The memory subsystem includes a burst DRAM device, a memory controller arranged to control the burst DRAM device in response to instructions received from the central processing unit, data format conversion circuitry arranged to convert between a data format readable by the burst DRAM device and a data format readable by the memory controller, and ECC circuitry arranged to encode a data word with an error correction code in response to a write instruction and to decode the data word and conduct error correcting and detecting in response to a read instruction.

REFERENCES:
patent: 5452261 (1995-09-01), Chung et al.
patent: 5577004 (1996-11-01), Leshem

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