Delta-sigma modulator with oscillation detect and reset circuit

Details Delta-sigma modulator with oscillation detect and reset circuit Delta-sigma modulator with oscillation detect and reset circuit

1989-10-27

1991-04-30

Pellinen, A. D.

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

341120, 341166, H03M 300

Patent

active

050122444

ABSTRACT:
An oscillation detect and reset circuit is provided for an analog modulator that includes a first stage of integration having a single ended differential amplifier (32) which is connected to the input of three stages of subsequent integration (40), (42) and (44), in a cascaded configuration. The output of the last stage of integration (44) is connected to the input of a one-bit quantizer (48). The output of the one-bit quantizer (48) is connected to the input of a current (50) feedback, which is connected between a summing node (36) and a negative voltage supply. The summing node (36) sums the current feedback with an input voltage for input to the amplifier (32). Switches (52), (54) and (56) are provided across the inputs and outputs of the integration stages (40), (42) and (44), respectively. The sensing of an unstable condition on the output of second stage of integration (40) is detected by oscillation detect comparators (60) and (62) to initiate a count cycle in a five-bit counter (66). The output of counter (66) generates a oscillation detect signal upon detection of an oscillation, which signal is output to the control inputs of the switches (52), (54) and (56), for thirty-two cycles of the analog modulator sampling frequency. This is a sufficient amount of time to allow the loop, which is a first order loop, to zero out during the reset period.

REFERENCES:
patent: 4107669 (1978-08-01), Tewksbury
patent: 4301446 (1981-11-01), Petit
patent: 4509037 (1985-04-01), Harris

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