Static information storage and retrieval – Floating gate – Particular biasing
Patent
1994-05-27
1995-05-16
Fears, Terrell W.
Static information storage and retrieval
Floating gate
Particular biasing
365218, 365900, 36518909, G11C 1300
Patent
active
054167388
ABSTRACT:
A flash EPROM memory cell array includes a plurality of flash cells arranged as a matrix of rows in columns of said cells. Each cell includes a single transistor. For each row of flash cells in the matrix, a corresponding bit line is connected to the drain region of each memory cell transistor in that row. For each column of flash cells, a corresponding wordline is connected to the control gate of each memory cell transistor in that column. Bias circuitry is provided for applying read bias voltages to the array for reading data from a selected cell in the matrix. The read bias circuitry includes means for applying a first control gate voltage to the wordline connected to the control gate of the selected cell and the second control gate voltage to the deselected wordlines. The first control gate voltage is positive and higher than the highest erased threshold voltage from the erased cell threshold voltage distribution and less than the lowest programmed threshold voltage from the programmed cell threshold distribution such that programmed cells in the selected row are shut off with insignificant drain current conduction. The second control gate voltage is less than the lowest erased threshold voltage such that erased cells connected to deselected wordlines are shut off with insignificant drain current conduction when the second control gate voltage is applied to the gates of the erased cells, even if the erased cells are overerased to negative threshold voltages.
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Alliance Semiconductor Corporation
Fears Terrell W.
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