Boots – shoes – and leggings
Patent
1992-09-03
1995-05-16
Teska, Kevin J.
Boots, shoes, and leggings
364491, 395921, G06F 1560
Patent
active
054167183
ABSTRACT:
In a circuit design support system, a logic minimizing unit receives data indicating a functional specification of a desired circuit and minimizes logical sequences of the desired circuit. A cell assignment unit assigns cells to each of minimized logical sequences determined by the logic minimizing unit and generates data on a circuit configuration of the desired circuit. The cells are logic units. A load/timing check unit receives the data on the circuit configuration and simultaneously executes a load check and a timing check. The load check determines whether or not the circuit configuration has a load driving ability within a tolerable load driving ability. The timing check determines whether or not the circuit configuration has a delay time of a signal within a tolerable delay time. A load adjustment unit executes a load adjustment of the circuit configuration on the basis of a result of the load check so that the load driving ability of the circuit configuration falls within the tolerable driving ability. A timing adjustment unit executes a timing adjustment of the circuit configuration on the basis of a result of the timing check so that the delay time of the circuit configuration falls within the tolerable delay time.
REFERENCES:
patent: 4484292 (1984-11-01), Hong et al.
patent: 4698760 (1987-10-01), Lembach et al.
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 5034899 (1991-07-01), Schult
patent: 5046017 (1991-09-01), Yuyama et al.
patent: 5105374 (1992-04-01), Yoshida
patent: 5119314 (1992-06-01), Hotta et al.
patent: 5168455 (1992-12-01), Hooper
patent: 5173864 (1992-12-01), Watanabe et al.
patent: 5191542 (1993-03-01), Murofushi
patent: 5208764 (1993-05-01), Rusu et al.
patent: 5208768 (1993-05-01), Simoudis
patent: 5210700 (1993-05-01), Tom
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5251147 (1993-10-01), Finnerty
patent: 5282148 (1994-01-01), Poirot et al.
Fujitsu Limited
Nguyen Tan
Teska Kevin J.
LandOfFree
Circuit design support system and circuit producing method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit design support system and circuit producing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit design support system and circuit producing method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-643101