Differential controlled delay elements and skew correcting detec

Electrical transmission or interconnection systems – With nonswitching means responsive to external nonelectrical... – Temperature responsive

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307605, H03K 513

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active

050121421

ABSTRACT:
A fully differential variable delay element for providing precision delays for use in digital phase-locked loops or the like. The delay in each stage is controlled by changing bias currents and the coupling of a capacitance load thereto, therby reducing the sensitivity of the delay element to electrical noise at low bias current levels (long delay times). Included is a circuit which substantially removes any skew in the differentially delayed signals from the delay element.

REFERENCES:
patent: 4476401 (1984-10-01), Lin
patent: 4496861 (1985-01-01), Bazes
patent: 4806804 (1989-02-01), O'Leary
"Design of PLL-Based Clock Generation Circuits", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr., 1987, pp. 255 through 261.
"Digitally Controlled Oscillator", IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Jun. 1989, pp. 640 through 645.

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