Computer system having a power conservation mode and utilizing a

Details Computer system having a power conservation mode and utilizing a Computer system having a power conservation mode and utilizing a

1995-12-26

1997-07-29

Ray, Gopal C.

Boots, shoes, and leggings

364707, G06F 132

Patent

active

056528957

ABSTRACT:
A digital system bus and its attached devices can be powered down and up using only its standard bus request and bus grant signal lines, without adding additional lines for control signals. By asserting the bus grant signal in the absence of the bus request signal, the bus arbiter device can signal other devices on the bus that is okay to enter a deep power conservation mode. In this mode, the devices on the bus may safely ignore bus activity--except they must monitor for a negation of the bus grant signal or for any system wake-up events for which they are responsible. Substantial power reduction can be achieved in such a mode, since clocks can be suspended to a large portion of the circuitry in the computer system. To wake up the non-arbiter devices, the bus arbiter simply negates the bus grant signal. To wake up the bus arbiter device, a non-arbiter device simply asserts its bus request signal. This deep power conservation mode may be enabled under software control, by means of software writing an enable bit in one or more of the bus devices.

REFERENCES:
patent: 4747041 (1988-05-01), Engle et al.
patent: 5167024 (1992-11-01), Smith et al.
patent: 5404544 (1995-04-01), Crayford
patent: 5404546 (1995-04-01), Stewart
patent: 5428790 (1995-06-01), Harper et al.
patent: 5452434 (1995-09-01), MacDonald
patent: 5471625 (1995-11-01), Mussemann et al.
patent: 5477476 (1995-12-01), Schanin et al.

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