Memory circuit, method of access, and method of preparation of d

Details Memory circuit, method of access, and method of preparation of d Memory circuit, method of access, and method of preparation of d

1995-03-29

1997-07-29

Asta, Frank J.

Boots, shoes, and leggings

395420, 395427, 395410, 364DIG1, G06F 1300

Patent

active

056528558

ABSTRACT:
A memory circuit, method of access, and method of preparation of data, which enable construction of a redundancy-free memory and hardware of a smaller circuit size, wherein of the data (C2, C6, -C2, -C2, -C6, C6, and C2) of a redundancy-ridden read only memory in which the same first data is stored a plurality of addresses, the same data existing at a plurality of addresses are assigned to a single address of the read only memory so as to prepare and record at predetermined addresses the data (C2, C6, -C6, and -C2) of the read only memory, provision is made of an address conversion circuit comprised of a decoder, two-input OR circuits for transforming the single address data of the read only memory to accessible addresses without requiring advance change of the address designations when there are address designations, and the single address of the memory is accessed and data output in accordance with the address designation.

REFERENCES:
patent: 5175808 (1992-12-01), Sayre
patent: 5390311 (1995-02-01), Fu et al.
patent: 5528176 (1996-06-01), Kean

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