Low latency cadence selectable interface for data transfers betw

Details Low latency cadence selectable interface for data transfers betw Low latency cadence selectable interface for data transfers betw

1996-05-24

1997-07-29

Auve, Glenn A.

395855, 395551, G06F 1342

Patent

active

056528485

ABSTRACT:
A bus interface with resources to selectively optimize burst mode data transfers from one bus to another through an automated selection and generation of a cadence. In one form, the cadence is selected based upon memory access latency characteristics, the relative widths of the busses, and the relative clock frequencies of the busses. The selected cadence is provided as a pacing ready signal to the bus receiving the transferred data.

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