Semiconductor memory device having hierarchical boosted power-li

Details Semiconductor memory device having hierarchical boosted power-li Semiconductor memory device having hierarchical boosted power-li

1996-05-15

1997-07-29

Fears, Terrell W.

Electricity: electrical systems and devices

Electric charging of objects or materials

Particulate matter

36518909, G11C 1300

Patent

active

056527306

ABSTRACT:
A DRAM includes an internal boosting circuit, a global power-line, a plurality of blocks, a row decoder, and a POR generating circuit. Each block includes word lines, local power-lines, AND gates, drive transistors, and word line drivers. The AND gate turns a corresponding drive transistor on/off in response to a power on reset signal /POR and a corresponding block select signal. Therefore, all the local boosted power-lines are connected to the global boosted power-line during a power on reset period, whereby all the local boosted power-lines are initially charged up to boosted power supply potential Vpp.

REFERENCES:
patent: 5579276 (1996-11-01), Yoon et al.

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