Memory through checking system with comparison of data word pari

Details Memory through checking system with comparison of data word pari Memory through checking system with comparison of data word pari

1984-08-21

1985-07-23

Smith, Jerry

Excavating

G06F 1108

Patent

active

045312133

ABSTRACT:
For use with a digital memory system that generates error correction code signals for storage with associated data words and for correction of detected error(s) in the associated data words when accessed, a system for through checking the accuracy of generation of the error correction codes and the decoding of error correction code is described. A data word parity signal is generated for storage with the associated data word and its associated check bit. When a data word is accessed, the read data word and its associated check bits are applied to error correction circuitry that results in a determination of whether or not any bits of the read data word are in error. Correction circuitry corrects those error in the read data word that are correctable. The corrected read data word is applied to a parity generator circuit that generates that parity of the corrected read data word. A comparison circuit compares the word parity calculated for the corrected read data word. Comparison indicates that the error correction system and through check system functioned properly, and failure of comparison indicates an error occurred in the throughput of the data word.

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Blazejewski, T. J., et al., "Mechanism for Checking Parity and Error Checking and Correction Functions in Processors and Processor-Linked Subsystems", IBM Technical Disclosure Bulletin, vol. 21, No. 12, May 1979, 4871-4877.

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