Scalable register file organization for a computer architecture

Details Scalable register file organization for a computer architecture Scalable register file organization for a computer architecture

1994-08-22

1996-04-30

Bowler, Alyssa H.

Boots, shoes, and leggings

395375, 395496, 395405, 364DIG1, 3642287, 3642318, 364247, 3642631, G06F 900

Patent

active

055133630

ABSTRACT:
A scalable register file including first and second micro-register files organized in a pipelined fashion to minimize the access time of the register file where there are a large number of registers or multiple functional units. Interposed between the first and second micro-register files are a first plurality of pipeline registers for storing the register contents fetched from the first micro-register file during a first pipeline cycle. A second plurality of pipeline registers are coupled to the second micro-register files for storing the register contents fetched from the second micro-register file during a second pipeline stage and those registers being stored in the first plurality of pipeline registers. The first plurality of pipeline registers are coupled to the bit lines of the second micro-register file. Enable logic is coupled to each of the first plurality pipeline registers to selectively present the contents of the first plurality of pipeline register to the second plurality of pipeline registers if there were contents stored in a first pipeline register during the first pipeline cycle. Alternatively, a multiplexer can be used to present the register contents stored in the first plurality of pipeline registers to the second plurality of pipeline registers.

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patent: 5440714 (1995-08-01), Wang
Su et al. "A Software Pipelining Based VLIW Architecture and Optimized Compiler" IEEE, 1990.
Ugurdag et al. "A VLIW Architecture Based on Shifting Register Files" IEE 1993.

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