SPS CCD memory system with serial I/O registers

Details SPS CCD memory system with serial I/O registers SPS CCD memory system with serial I/O registers

1977-10-20

1979-05-01

Fears, Terrell W.

Static information storage and retrieval

Addressing

Byte or page addressing

307238, G11C 1140

Patent

active

041527801

ABSTRACT:
An organization of serial-parallel-serial (SPS) charged-coupled-device (CCD) memory arrays or blocks into a memory system is disclosed. Each memory block is comprised of an N-bit input register, an N-bit output register, N S-bit parallel registers and an N-bit I/O register. Data is bit-serially entered into the input register at a frequency F.sub.0 is bit-parallelly shifted through the parallel registers and simultaneously into the output register and the I/O register at a frequency F.sub.0 /N. Addressed read data are captured by the I/O register and are circulated continuously therein independently of the recirculation process performed by the output register, input register such that if I/O transfer rates are lower than the allowable refresh frequency of the charged-coupled-devices of the memory block, and if one or more refresh cycles are utilized, the addressed read data always remains available in the I/O register. Data is written into consecutively numerically increasing memory blocks such that a consecutive bit stream of data is loaded into the consecutive stages of the consecutive I/O registers during the read operation. This ensures an uninterrupted consecutive output bit stream of the addressed read data independently of refresh cycle shifting of the stored data bits within the recirculation loop.

REFERENCES:
patent: 3772658 (1973-11-01), Sarlo
patent: 3953837 (1976-04-01), Cheek, Jr.

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