Non-scan design-for-testability of RT-level data paths

Details Non-scan design-for-testability of RT-level data paths Non-scan design-for-testability of RT-level data paths

1994-06-30

1996-04-30

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, 371 22, G06F 1750

Patent

active

055131239

ABSTRACT:
Non-scan design-for-testability methods for making register-transfer-level data path circuits testable include using EXU S-graph representation of the circuits. Loops in the EXU S-graph are made k-level controllable/observable to render the circuit testable without having to scan any flip-flops or break loops directly. Moreover, the resultant circuit is testable at-speed.

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