Compaction/expansion logic

Details Compaction/expansion logic Compaction/expansion logic

1977-07-11

1979-05-01

Miller, Charles D.

Registers

Systems controlled by data bearing records

Time analysis

178 26A, H03K 1300

Patent

active

041525825

ABSTRACT:
A system of encoding a fixed-level character format for transmission in a format of variable or multi-level character lengths is disclosed. A fixed-level character format, e.g., an 8-bit character length of high to low ordered bits 2.sup.7 -2.sup.0, received by a transmitting communications line terminal from an associated processor at a transmitting site is examined, a "Short" bit 2.sup.S is generated, and depending upon the number of higher order bits that are 0 bits and whether the remaining bits are an odd or an even number of 1 bits, a new variable or multi-level character is generated and transmitted on the communications line along with the associated "Short" bit. The reverse procedure is utilized at the receiving communications line terminal to regenerate the fixed-level character format utilized by the associated processor at the receiving site. Through a statistical analysis of the frequency of transmission of individual characters of the fixed-level character format that is used by the processors the most frequently used characters are transmitted in a shortened form such that total message block transmission time is substantially reduced.

REFERENCES:
patent: 3008127 (1961-11-01), Bloch
patent: 3016527 (1962-01-01), Gilbert
patent: 3271517 (1966-09-01), De Rosa

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