Pause apparatus for a memory controller with interleaved queuing

Details Pause apparatus for a memory controller with interleaved queuing Pause apparatus for a memory controller with interleaved queuing

1981-12-17

1985-12-10

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 900

Patent

active

045584290

ABSTRACT:
A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for storing memory requests to be processed. The memory controller further includes control apparatus connected to monitor bus activity. In response to certain bus activity conditions occurring during multiword transfer operations, the control apparatus operates to lengthen the time between successive multiword transfers of data to the bus so as to ensure that new requestors having lower priorities than a memory controller gain access to an available queue notwithstanding the amount of bus delay incurred in transmitting their memory requests.

REFERENCES:
patent: 4236203 (1980-11-01), Curley et al.
patent: 4344132 (1982-08-01), Dixon et al.
patent: 4451880 (1984-05-01), Johnson et al.

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