Triple-implanted drain in transistor made by oxide sidewall-spac

Details Triple-implanted drain in transistor made by oxide sidewall-spac Triple-implanted drain in transistor made by oxide sidewall-spac

1989-02-23

1989-10-31

James, Andrew J.

357 90, H01L 2978

Patent

active

048781002

ABSTRACT:
A transistor for VLSI devices made by the sidewall-spacer method uses a reach-through implant both before and after the sidewall spacer is defined. An arsenic implant self-aligned with the gate prior to the sidewall oxide, then a phosphorus implant and lateral diffusion performed after the sidewall oxide etch creates a reduced impurity concentration and graded junction for the reach-through implanted region beneath the oxide sidewall spacer. An arsenic implant after the sidewall spacer is in place provides heavily-doped low-resistance source/drain regions.

REFERENCES:
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patent: 4342149 (1982-08-01), Jacobs et al.
patent: 4356623 (1982-11-01), Hunter
patent: 4566175 (1986-01-01), Smayling et al.
patent: 4599118 (1986-07-01), Han et al.
IBM Technical Disclosure Bulletin, vol. 15, #6, pp. 1884-1885, by Krich et al., Nov. 1972.
Takeda et al., IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 611-618.

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