Method of manufacture of a split gate flash EEPROM memory cell

Details Method of manufacture of a split gate flash EEPROM memory cell Method of manufacture of a split gate flash EEPROM memory cell

1994-11-23

1996-04-30

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 36, 437 44, H01L 218247

Patent

active

055125034

ABSTRACT:
A manufacturing process for a MOSFET device on a lightly doped semiconductor substrate comprises forming a dielectric layer on the substrate, a floating gate layer over the dielectric layer, a sacrificial layer on the floating gate layer, and a split-gate channel mask patterned with openings over the sacrificial layer. Etch the sacrificial layer to remove material beneath mask openings and etch the floating gate layer to remove material beneath mask openings to form a self-aligned channel mask for ion implanting the source/drain regions of the device. Overetch the floating gate layer to form a floating gate and ion implant doped source/drain regions. Remove the channel mask and the remainder of the sacrificial layer. Form a drain side mask and ion implant a drain side N- region into the substrate. Form a blanket interpolysilicon dielectric layer, a deposit of a control gate layer over the interpolysilicon layer with a control gate mask, and etch the control gate layer through the control gate mask openings. Then, remove the control gate mask.

REFERENCES:
patent: 4868629 (1989-09-01), Eitan
patent: 5194925 (1993-03-01), Ajika et al.
patent: 5280446 (1994-01-01), Ma et al.
patent: 5286665 (1994-02-01), Muragishi et al.
"128L Flash EEPROM Using Double-Poly-Silicon Technology" IEEE Solid State Circuit vol. SC-22, No. 5, pp. 676-683, Oct. 1987.

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