Semiconductor memory device with cache memory addressable by blo

Details Semiconductor memory device with cache memory addressable by blo Semiconductor memory device with cache memory addressable by blo

1988-08-05

1990-05-15

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Plural blocks or banks

365240, 36523008, G11C 700

Patent

active

049263854

ABSTRACT:
A semiconductor memory includes a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines. A plurality of memory cells are arranged at intersections of the bit lines and the word lines, respectively. Word line selecting circuitry selects one of the word lines responsive to a row address and reads out to each of the bit lines information stored in the memory cell associated with the selected word line. A plurality of sense amplifiers are associated with corresponding rows of the memory for detecting and amplifying the information stored in respective memory cells. A first column selector circuit selects the sense amplifiers corresponding to a column address when the column address is applied and reads information held in the sense amplifier. Blocks are formed by dividing the memory cell array into groups of bit lines, each of the groups comprising a predetermined number of bit lines with block information transferred simultaneously from corresponding ones of the groups of bit lines of a selected block when the column address corresponding to the selected block is applied. Data registers hold information of an associated block. A second column selector reads data corresponding to the column address from the data register when the column address is applied.

REFERENCES:
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4577293 (1986-03-01), Matick et al.
patent: 4725945 (1988-02-01), Kronstadt et al.
patent: 4755974 (1988-07-01), Yamada et al.
patent: 4803621 (1989-02-01), Kelly

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