Boots – shoes – and leggings
Patent
1977-12-09
1982-11-02
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 930, G06F 1306
Patent
active
043576567
ABSTRACT:
In a data processing system having a main memory containing addressable main memory storage locations, and also having a processor with a cache memory containing addressable cache memory storage locations, signals representative of predetermined addressable cache memory storage locations desired to be intentionally disabled by an operator of the data processing system are compared with signals representative of an addressable main memory storage location being addressed by the processor during the execution of a program instruction. The data processing system is then caused to access the addressable main memory storage location when the signals representative of the predetermined addressable cache memory storage locations are in a predetermined fixed relationship with the signals representative of the addressable main memory storage location being addressed by the processor during the execution of the program instruction. When selected cache memory storage locations are thereby intentionally disabled, remaining enabled cache memory storage locations can be diagnosed by diagnostic program instructions which are loaded into main memory storage location by by-passing the selected cache memory storage locations. The enabled portions can then be tested by executing the diagnostic program instructions so loaded.
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Saltz Warren L.
Vezza Anthony S.
Digital Equipment Corporation
Fisher Arthur W.
Heckler Thomas M.
Paciulan Richard J.
Shaw Gareth D.
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