Leading 0/1 anticipator (LZA)

Details Leading 0/1 anticipator (LZA) Leading 0/1 anticipator (LZA)

1988-10-07

1990-05-15

Harkcom, Gary V.

Boots, shoes, and leggings

36471504, 36471510, G06F 738

Patent

active

049263692

ABSTRACT:
A method and system for performing a leading 0/1 anticipation (LZA) in parallel with the floating-point addition of two operands (A and B) in a computer to significantly reduce the Addition-Normalization time. A combinational network is used to process appropriate XOR (P), AND (G) and NOR (Z) state signals resulting from the comparison of the bits in corresponding bit positions of the operands (A and B), starting with the most significant bit (MSB) side of the addition. The state of the initial state signal is detected and shift amount signals are produced and counted for each successive state signal detected, as long as the state remains TRUE. When the state becomes NOT TRUE, adjustments are made depending on the initial state and the successive state, and production of the shift amount signals is halted and an adjustment signal is produced. To determine the exponent of the sum of the floating-point addition, the shift amount count is summed with the adjustment signal. The latter sum will be the exponent of the sum of the operands thus providing a normalized result. The adjustment signal may be based on the CARRY at the NOT TRUE bit position, and the state at the NOT TRUE position may be used to determine whether the result of the addition is positive or negative. In addition to a serial network, an implementing network of a parallel form which accepts appropriate state inputs as blocks of n bits in length, is disclosed, along with certain special implementations.

REFERENCES:
patent: 3831012 (1974-08-01), Tate et al.
patent: 4794557 (1988-12-01), Yoshida et al.

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