Semiconductor memory device having extended margin in latching i

Details Semiconductor memory device having extended margin in latching i Semiconductor memory device having extended margin in latching i

1996-09-12

1998-05-05

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523008, 365233, 36518905, 365194, G11C 800, G11C 700

Patent

active

057485534

ABSTRACT:
A semiconductor memory device includes an internal clock signal generating section for generating an internal clock signal from an external clock signal. A latch section includes an address latching circuit for latching an inputted address, a command latching circuit for latching an inputted command and a write data latching circuit for latching an inputted write data. A state setting section controls the address latching circuit, the command latching circuit and the write data latching circuit based on an address key latched by the address latching circuit and a mode setting command latched by the command latching circuit such that a time difference is selectively extended between a first timing of the internal clock signal and a second timing for each of the address, the command and the write data to be changed.

REFERENCES:
patent: 5566108 (1996-10-01), Kitamura
patent: 5581512 (1996-12-01), Kitamura

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