Triple redundant fault-tolerant register

Details Triple redundant fault-tolerant register Triple redundant fault-tolerant register

1989-04-11

1991-07-09

Smith, Jerry

Excavating

307464, G06F 1118

Patent

active

050311808

ABSTRACT:
A fault tolerant register employing triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The fault tolerant register includes a single master multiplexer, three slave multiplexers connected in parallel to the output of the master multiplexer and three voting circuits positioned in feedback paths of the slave multiplexers. The slave multiplexers provide triple redundant storage for the data and the voting circuits correct any data that might become disrupted. The fault tolerant register of the present invention provides greatly improved SEU tolerance without a large increase in circuit area or without resorting to error correction and its attendant scrubbing process.

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patent: 4748594 (1988-05-01), Iida

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