Improved ratio decoder for use in a non-restoring binary divisio

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G06F 752

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050311387

ABSTRACT:
An essentially symmetrical ratio decoder which covers all areas in both the positive and negative regions with only a small number of noted exceptions. Multiple boundaries were selected such that the positive and negative regions were symmetrical with only a small number of exceptions. Using these boundaries, an essentially symmetrical, unified ratio decoder was constructed using only about one-half of the integrated circuit real estate of conventional ratio decoder pairs. By decoding the sign bit from the ratio decoder adder, the ratio decoder recognizes the exceptional areas and handles them accordingly.

REFERENCES:
patent: 3591787 (1968-01-01), Freiman et al.
patent: 3621218 (1971-12-01), Nishimoto
patent: 3852581 (1974-12-01), Reynard et al.
patent: 4722069 (1988-01-01), Ikeda
IBM Technical Disclosure Bulletin, vol. 23, No. 8, 1/81, pp. 3811-3814, entitled "4-2 Carry-Save Adder Module" by A. Weinberger.
IBM Technical Disclosure Bulletin, vol. 20, No. 8, 2/78, pp. 3594-3597, entitled "4-2 Carry-Save Adder Implementation Using Send Circuits", by D. T. Shen and A. Weinberger.
IBM Technical Disclosure Bulletin, vol. 14, No. 11, 4/72, pp. 3279-3281, entitled "Uniform 2 Bits Quotients Binary Division by Carry-Save Adders", by K. G. Tan.

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