Semiconductor memory device having two layers of bit lines arran

Details Semiconductor memory device having two layers of bit lines arran Semiconductor memory device having two layers of bit lines arran

1994-11-23

1996-10-08

Popek, Joseph A.

Static information storage and retrieval

Interconnection arrangements

365 51, 365206, G11C 506

Patent

active

055638201

ABSTRACT:
Bit lines which are adjacent to each other are connected to bit line signal input/output lines which are not adjacent to each other, via through holes. By this connection, data input/output lines, shield lines and a global word line are arranged between the through holes, whereby the distance between the through holes can be widened, minimum space between the bit lines can be widened, and therefore, higher integration of the memory array is realized.

REFERENCES:
patent: 4907203 (1990-03-01), Wada et al.
patent: 5214601 (1993-05-01), Hidaka et al.
patent: 5280441 (1994-01-01), Wada et al.
"Bit Line Configuration Suitable for Very High Speed SRAM--T-Shaped Bit Line Configuration and Application to BICMOS 256K TTL SRAM", T. Kenkyukai et al., pp. 117-123, Jun. 21, 1991.
"A 5.8-NS 256-KB BICMOS TTL SRAM With T-Shaped Bit Line Architecture", Toru Shiomi et al., IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993.
"New Bit Line Architecture for Ultra High Speed SRAMS" Shiomi et al., IEEE 1991 Custom Integrated Circuits Conference.

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