Semiconductor memory device having error correcting circuit and

Details Semiconductor memory device having error correcting circuit and Semiconductor memory device having error correcting circuit and

1988-11-15

1991-03-26

Atkinson, Charles E.

Excavating

371 402, 371 511, G06F 1110, G11C 2900

Patent

active

050035428

ABSTRACT:
In a semiconductor memory device having an error correcting circuit, a pair of bit lines and inverted bit lines are connected to the inputs of first and second inverting amplitude circuits through a first and second N channel MOS transistors, respectively, and the output of the first inverting amplitude circuit is connected to the bit line through a third transistor and the output of the second inverting amplitude circuit is connected to the inverted bit line through a fourth transistor. When an error of information of any bit line pair is detected by an error detecting circuit, the first and second N channel MOS transistors are turned off and each bit line pair is separated from the input of the first and second inverting amplitude circuits and, as a result, information of a bit line pair is rewritten by the output of the first and second inverting amplitude circuits.

REFERENCES:
patent: 4070648 (1978-01-01), Mergenthaler et al.
patent: 4296494 (1981-10-01), Ishikawa et al.
patent: 4592024 (1986-05-01), Sakai et al.
patent: 4712197 (1987-12-01), Sood
patent: 4748487 (1988-05-01), Uchida et al.
patent: 4748627 (1988-05-01), Ohsawa
Junzo Yamada et al., "A Submicron 1 Mbit Dynamic RAM with a 4-Bit-at-a-Time Built-In ECC Circuit", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, Oct. 1984, pp. 627-633.
Junzo Yamada, "Selector-Line Merged Built-In ECC Technique for DRAM's", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct., 1987, pp. 868-873.

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