Method of transmitting data at full bandwidth within a synchrono

Details Method of transmitting data at full bandwidth within a synchrono Method of transmitting data at full bandwidth within a synchrono

1989-06-22

1991-03-26

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375111, 371 1, 307601, 307602, H04L 700

Patent

active

050035371

ABSTRACT:
The invention expands the period of data stabilization between state devices to be 1.5 times the cycle time minus the clock skew. The invention requires that a clock signal (hereinafter "forwarded clock") be sent with data to the receiving subsystem. Such data is received by a capture latch, which is operated by special logic that receives the forwarded clock, and then proceeds to an ordinary state device in the receiving subsystem that is running synchronously with the receiving subsystem. This state device nominally captures the data 1.5 cycles after it was sent from a state device in the sending subsystem.

REFERENCES:
patent: 4811364 (1989-03-01), Sager et al.
patent: 4839907 (1989-06-01), Saneski
patent: 4847867 (1989-07-01), Nasu et al.
patent: 4873703 (1989-10-01), Crandall et al.

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