Precharge circuitry and bus for low power applications

Details Precharge circuitry and bus for low power applications Precharge circuitry and bus for low power applications

1989-06-26

1991-03-26

Teska, Kevin J.

Boots, shoes, and leggings

364200, 364900, 368 10, G06F 1300, G06F 1338

Patent

active

050035010

ABSTRACT:
A low-power integrated circuit clock/calendar, wherein separate data busses are used for the time data and the alarm data. Conditional logic is used to only compare seconds bits (unless a match occurs, in which case higher-order bits are then compared). Thus, charging and discharging of the data busses (which carry the time data) occurs only when a data transition is occurring. A special clocked latch circuit is used to hold the potential of each line of the time data bus constant, except when the data on the bus is actually changing. These innovations help to provide extremely long battery lifetime, since charge is not consumed by unnecessarily charging and discharging busses. Preferably this bus architecture is combined with a low-power logic architecture.

REFERENCES:
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patent: 4238832 (1980-12-01), Tsuzuki et al.
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patent: 4387420 (1983-06-01), Singhi et al.
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patent: 4424567 (1984-01-01), Yasutake
patent: 4602347 (1986-07-01), Koyama
patent: 4677541 (1987-06-01), Singhi
patent: 4851987 (1989-07-01), Day
patent: 4891776 (1990-01-01), Kuroki et al.
DS1215 Preliminary Data Sheet from 1987 Data Book of Dallas Semiconductor.

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