Closed loop address

Details Closed loop address Closed loop address

1978-11-30

1980-10-07

Zache, Raulfe B.

Boots, shoes, and leggings

371 21, 371 24, G06F 1100, G11C 2900

Patent

active

042272440

ABSTRACT:
An apparatus for enabling a central processing unit (CPU) to directly read the address transferred to a memory module to permit the CPU to test the address circuitry of the memory module without actually referencing an addressable location of the memory array within the memory module. A status register located within the memory module has two bit positions assigned to controlling the closed loop address capability. If the two assigned bit positions contain binary zeroes, the memory module operates normally by using each address received to address one addressable location of the memory array of the memory module. If one of the assigned bit positions contains a binary one, subsequent read commands cause the memory not to access the memory arrays but to return the portion of the address corresponding to the bit position containing the binary one (i.e., one bit position causes part of the address to be returned whereas the other bit position causes the remainder of the address to be returned) to the requesting CPU as if it were data read from the contents of the specified addressable location, thus permitting the CPU to directly verify the correct operation of the addressing circuitry of the memory module. Since the assigned bit positions of the status register may be easily altered under software control, the closed loop address capability may be rapidly and automatically invoked to periodically verify the correct operation of the addressing circuitry of the memory module.

REFERENCES:
patent: 3228000 (1966-01-01), Collis
patent: 3270318 (1966-08-01), Strawbridge
patent: 3665175 (1972-05-01), Bouricius et al.
patent: 3982111 (1976-09-01), Lerner et al.

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