Method for making IC die with dielectric isolation

Details Method for making IC die with dielectric isolation Method for making IC die with dielectric isolation

1989-03-24

1990-05-15

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 65, 437 66, 437 67, 437227, 437228, 437911, 357 56, H01L 2176, H01L 2180, H01L 2186, H01L 2980

Patent

active

049258087

ABSTRACT:
The method includes forming in one surface of an N+ silicon wafer a matrix of uniformly deep V-shaped grooves, growing one SiO.sub.2 over the one surface and the walls of the grooves, forming over the opposite wafer surface a thick self-supporting polycrystalline layer, progressively removing portions of the original silicon wafer until the bottoms of the grooves are detected to leave separate patches of the original N+ silicon wafer material and then growing a thin (e.g. 6 microns) P-doped layer of epitaxial silicon on the exposed N+ silicon layer patch portions now isolated and defined by the grooves. A figure-eight pattern of trenches is formed in each silicon island completely through the P epitaxial layer and each of the underlying N+ buried patches but stopped at the SiO.sub.2 layer. An N+ plug is formed through the epitaxial layer to each N+ patch. Metal conductors complete the formation of a JFET transistor in each island bounded and defined by one of the closed loops or annular portions of the figure-eight-patterned trenches. The wafer is then sawed apart along all the V-shaped grooves providing a plurality of IC die, each having two dielectrically isolated JFET transistors.

REFERENCES:
patent: 3381182 (1968-04-01), Thornton
patent: 3411200 (1968-11-01), Formigoni
patent: 3954522 (1976-05-01), Roberson
patent: 3966577 (1976-06-01), Hochberg
patent: 4408386 (1983-10-01), Takayashiki et al.
patent: 4449284 (1984-05-01), Shimbo
patent: 4501060 (1985-02-01), Frye et al.
patent: 4567646 (1986-02-01), Ishikawa et al.
patent: 4638552 (1987-01-01), Shimbo et al.
patent: 4851078 (1989-07-01), Short et al.

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