Process independent design for gate array devices

Details Process independent design for gate array devices Process independent design for gate array devices

1993-10-06

1996-10-08

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, G06F 1750

Patent

active

055638015

ABSTRACT:
A unique gate array cell and ASIC library development methodology is taught which require no new simulations or new place and route to port a given device design to a same generation process technologies which are available from different vendors. This methodology make use of the minimum design rules from different vendors without reroute of the physical database. This methodology equalizes the functionality and timing characteristics of the macrocell library on a plurality of alternate sources.

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