Semiconductor device having a high resistivity layer in direct c

Details Semiconductor device having a high resistivity layer in direct c Semiconductor device having a high resistivity layer in direct c

1984-10-26

1985-12-10

Munson, Gene M.

357 41, 357 54, 357 59, H01L 2702, H01L 2934, H01L 2904

Patent

active

045583439

ABSTRACT:
This invention provides a semiconductor device, which has a high impurity concentration diffusion region such as a drain diffusion region and a resistor comprising a polycrystalline silicon layer (which may be a load of a driver MOS transistor), and in which part of the resistor is in direct contact with the high impurity concentration diffusion region. This invention also provides a method of manufacturing a semiconductor device, which comprises the steps of forming a gate electrode and drain and source diffusion regions along the principal surface of a semiconductor substrate, then forming a polycrystalline silicon resistor layer of a comparatively low impurity concentration such that it is in direct contact with a diffusion region, and subsequently causing impurity diffusion from the diffusion region through thermal treatment to obtain ohmic contact between the diffusion region and resistor layer.

REFERENCES:
patent: 3519901 (1970-07-01), Bean et al.
patent: 4110776 (1978-08-01), Rao et al.
patent: 4146902 (1979-03-01), Tanimoto et al.
patent: 4209716 (1980-06-01), Raymond, Jr.
patent: 4246593 (1981-01-01), Bartlett
patent: 4270137 (1981-05-01), Coe
patent: 4322824 (1982-03-01), Allan
"Two Static 4K Clocked and Nonclocked RAM Designs", T. R. O'Connell et al., IEEE J. Solid-State Circuits, vol. SC-12, No. 5, pp. 497-501, Oct. 1977.

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