Multi-rate branch metric processor for maximum-likelihood convol

Details Multi-rate branch metric processor for maximum-likelihood convol Multi-rate branch metric processor for maximum-likelihood convol

1982-10-04

1985-02-19

Smith, Jerry

Excavating

G06F 1112

Patent

active

045009945

ABSTRACT:
A branch metric processor for use in a maximum-likelihood convolutional decoder accepts a set of soft-decision symbols, an indicator of a level of quantization thereof and a set of erase control signals and generates branch metrics for base code rates of 1/3 and 1/2. The apparatus represents a substantial reduction in complexity over prior art devices. Erasure of selected symbols allows the processor to generate branch metrics for higher code rates and is advantageous in very low code rate applications.

REFERENCES:
patent: 4038636 (1977-07-01), Doland
patent: 4130818 (1978-12-01), Snyder, Jr.
patent: 4240156 (1980-12-01), Doland
Peterson and Weldon, Error-Correcting Codes, second edition. The MIT Press, 1972, pp. 392-425.
Forney, "The Veterbi Algorithn", Proc. IEEE, vol. 61, pp. 268-278, Mar. 1973.

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