Pipelined digital processor arranged for conditional operation

Details Pipelined digital processor arranged for conditional operation Pipelined digital processor arranged for conditional operation

1982-07-23

1985-09-03

Thomas, James D.

Boots, shoes, and leggings

G06F 738

Patent

active

045396353

ABSTRACT:
A pipelined digital processor includes a common data and control bus and a source (100 or 105) of instructions and data words. An arithmetic section (110) processes one data word with another data word through selected processing subsections (112, 115, 116) performing operations according to an expression, thereby producing a resultant data word and a status signal. A destination (105) receives the resultant data word from the arithmetic section. Control circuits (IR-C) decode a single conditional instruction for controlling performance of a specific condition test during a first subsequent processor cycle (i.e., i+2). The control circuits further decoding another instruction word during the first subsequent processor cycle for controlling all processing sections operations during a second subsequent processor cycle (i.e., i+3). A circuit (215 and 122) compares the status signal with the specific condition information included in the conditional instruction for selectively disabling at least one section while enabling at least one other section of the digital processor during the second subsequent processor cycle.

REFERENCES:
patent: 3401376 (1968-09-01), Barnes
patent: 3577190 (1971-05-01), Cocke et al.
patent: 3771138 (1973-11-01), Celtruda
patent: 3840861 (1974-10-01), Amdahl
patent: 3875391 (1975-04-01), Shapiro
patent: 4075688 (1978-02-01), Lynch
IBM Journal of R and D, "The IBM Sys/360 Model 91: Machine Philosophy and Instr-Handling", pp. 8-24, 1/1967.
Intel 2920 Assembly Language Manual, 1979, pp. i and 3-8.

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