Substrate bias generator with power supply control means to sequ

Details Substrate bias generator with power supply control means to sequ Substrate bias generator with power supply control means to sequ

1985-05-09

1987-06-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 307297, 307592, 307594, H03K 3353

Patent

active

046706682

ABSTRACT:
A bias generator circuit includes a first high voltage for biasing a N-well region and a second delayed and lower voltage biasing a source region of a P-channel field-effect transistor so as to increase latch-up immunity. The generator circuit includes a high voltage generator and a multiplier circuit responsive to a power supply voltage for generating a first voltage level for biasing the N-well region. A delay network is responsive to the first voltage for generating a delay voltage. A level detection circuit is responsive to the delay voltage and the power supply voltage for generating a control signal when the delayed voltage reaches a predetermined level. A control device is responsive to the control signal for generating a second voltage for biasing the source region of the P-channel field-effect transistor. The second voltage level is delayed and lower than the first voltage level so that the PN junction is reverse biased to increase latch-up immunity.

REFERENCES:
patent: 4039869 (1977-08-01), Goldman et al.
patent: 4151425 (1979-04-01), Cappa
patent: 4233672 (1980-11-01), Suzuki et al.
patent: 4281260 (1981-07-01), Moegen et al.
patent: 4300061 (1981-11-01), Mihalich et al.
patent: 4463270 (1984-07-01), Gordon
patent: 4473758 (1984-09-01), Huntington
patent: 4549096 (1985-10-01), Hoffmann
patent: 4571505 (1986-02-01), Eaton, Jr.

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