Method of making and testing an integrated circuit

Details Method of making and testing an integrated circuit Method of making and testing an integrated circuit

1988-05-16

1990-05-15

Arbes, Carl J.

Metal working

Method of mechanical manufacture

Electrical device making

29407, 29846, H05K 330

Patent

active

049245899

ABSTRACT:
Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By CAD means, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD means. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.
The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure. The tester surfaces traces are then connected, by means of multiplexers, to a conventional tester signal processor.

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