Method and apparatus for enabling intelligent I/O subsystems usi

Details Method and apparatus for enabling intelligent I/O subsystems usi Method and apparatus for enabling intelligent I/O subsystems usi

1995-06-15

1998-03-31

Shin, Christopher B.

395310, 395821, 395309, 395280, 395287, G06F 1338

Patent

active

057348472

ABSTRACT:
A processor for creating an intelligent input/output subsystems which includes a local processor coupled to a local system bus; a local memory controller coupled to the local system bus that enables access to a memory from the local system bus; a bus bridge having a first bus interface coupled to a first component bus; a second bus interface coupled to a second component bus, the bus bridge including means for creating an address space which is private to the secondary component bus such that the bridge will not send any address found in the private address space upstream to the primary component bus; and address translation means coupled to the local system bus and the bus bridge for translating addresses between the local system bus and the second component bus. A method for creating private devices comprising the steps of configuring the bus bridge to disable the assertion by the first component of a component select signal on the second component bus; creating an address space which is private to the secondary component bus such that the bridge will not send any address found in the private address space upstream to the primary component bus; translating the private address to a local system address in a local system address space; and translating a local system address contained in the local system address space to the private address.

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