Bidirectional power FET with shorting-channel off state

Details Bidirectional power FET with shorting-channel off state Bidirectional power FET with shorting-channel off state

1984-05-09

1985-12-10

Clawson, Jr., Joseph E.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307252B, 307304, 357 234, 357 39, 357 41, 357 43, 357 55, 357 86, H03K 1760

Patent

active

045582432

ABSTRACT:
A gating technique during the OFF state is disclosed for split gate bidirectional power FET structure 2, including AC application. First and second conduction channels 14 and 16 are gated OFF to stop conduction. One of the channels such as 14 is then gated back ON to short an otherwise forward biased junction 18 between a common drift region 4 and the respective channel-containing region 6, to prevent minority carrier injection and consequent bipolar action. OFF state voltage is blocked by the reverse biased junction 20 between the drift region 4 and the other channel-containing region 8. The OFF state voltage blocking capability is higher without the forward biased injection junction 18.

REFERENCES:
patent: 4199774 (1980-04-01), Plummer
patent: 4414560 (1983-11-01), Lidow
patent: 4487457 (1984-12-01), Janutka
patent: 4488068 (1984-12-01), Janutka
J. Plummer et al., "Insulated Gate Planar Thyristors," IEEE Trans. on Elec. Dev., vol. ED-27, #2, Feb. 1980.

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