Multiple port high speed register file with interleaved write po

Details Multiple port high speed register file with interleaved write po Multiple port high speed register file with interleaved write po

Filed on

1995-06-02

Date issued

1997-07-01

Examiner

Pan, Daniel H.

Patent Class

Boots, shoes, and leggings

Other Related Categories

395454, 395484, 395391, 364DIG1, 364DIG2, G06F 930, G06F 1204, G06F 1206

Type

Patent

Status

active

Patent number

056447809

Description

ABSTRACT:
A high speed register file is provided for use with Very Long Word Instruction (VLIW) and N-way superscaler processors. The high speed register file includes a selected number of copies of a general purpose register (GPR) building block. The GPR building block includes at least two interleaved sub-banks of registers. Each of the sub-banks includes a number N of write ports and a number M of read ports. The sub-banks are interleaved by write ports and have non-interleaved read ports.

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