System for addressing a multibank memory system

Details System for addressing a multibank memory system System for addressing a multibank memory system

1985-05-24

1988-02-23

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 1210

Patent

active

047275103

ABSTRACT:
The preferred embodiment shown involves forming the memory system of B memory banks, where B is preferably a prime number, but may be a nonbinary number, i.e., B=2.sup.X, where X is a positive integer, and where the requested address=(Q+R)B. The address translation system for each requestor seeking access to the memory system includes a ROM and an adder. The ROM is comprised of two ROMs, Q ROMa and Q ROMb. ROMb stores in successive memory locations a first portion Qb of the memory system address and Q ROMa stores in successive memory locatins a second portion Qa of the memory system address. An adder sums the data, Qa+Qb, stored in the addressed memory locations of Q ROMa and Q ROMb while Q ROMa stores in successive memory locations a Bank R portion that specifies the one of the B banks in which the sum Qa+Qb addresses the selected memory address in the selected memory bank of the memory system.

REFERENCES:
patent: 4189767 (1980-02-01), Ahuja
patent: 4346438 (1982-08-01), Potash et al.
patent: 4598362 (1986-07-01), Kinzo et al.

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