Digital scaling circuitry with truncation offset compensation

Details Digital scaling circuitry with truncation offset compensation Digital scaling circuitry with truncation offset compensation

1985-03-25

1988-02-23

Kemeny, Emanuel S.

Boots, shoes, and leggings

364724, 364715, 375 26, G06F 738

Patent

active

047275065

ABSTRACT:
A scaling circuit for scaling PCM signals by factors less than one includes a bit-shift and truncating circuit. Roundoff error compensating circuitry adds an offset value to the samples to be scaled by the bit-shift circuitry to compensate for errors produced by truncation without rounding. The offset values are dithered to increase the apparent resolution of the system.

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B. Gold and C. M. Rader, Digital Processing of Signals, McGraw-Hill Book Co. N.Y., 1969, pp. 98-131.

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