Memory system with error detection and correction

Excavating

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G06F 1110

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active

044647557

ABSTRACT:
A memory system comprised of M memory modules where M-1 of the modules are for storing data bits and the Mth modules is for storing system parity bits corresponding to the data bits stored in the other M-1 modules. Each module has R.multidot.C bit locations organized into W internal words of L bits and includes a parity array for storing one parity bit for each internal word, where L is greater than 1, and RC=WL. Each module includes means for reading an internal word and for reading-out a particular subset of the L bits of that internal word. Each module includes means for checking the parity of a selected internal word and for producing a first parity signal indicating whether or not it is correct. The memory system includes means for checking the parity of the selected subsets read out from the M modules and for producing a system parity signal indicating whether the parity of the M subsets is correct. When the first parity signal and the system parity signals indicate the presence of parity errors the subset read out from a module whose first parity signal indicates the presence of a parity error is corrected.

REFERENCES:
patent: 3972033 (1976-07-01), Cislaghi et al.
patent: 4038537 (1977-07-01), Cassarino, Jr. et al.
patent: 4044328 (1977-08-01), Herff
patent: 4360917 (1982-11-01), Sindelar et al.

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